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Differential Clock Divider Evaluation Border

Overview

The NB7V32M is a differential divide-by-2 Clock divider with asynchronous reset. The differential Clock inputs incorporate internal 50-ohm termination resistors and will accept LVPECL, CML and LVDS logic levels. The NB7V32M produces a divide-by-2 output copy of an input Clock operating up to 10GHz with minimal jitter. The Reset pin is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the Reset allows for the synchronization of multiple NB7V32M's in a system. The 16mA differential CML output provides matching internal 50-ohm termination which guarantees 400mV output swing when externally receiver terminated with 50-ohm to VCC.

  • Test & Measurement, ATE
  • Instrumentation, Networking

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Differential Clock Divider Evaluation Border

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Technical Documentation

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EVBUM2185/D

0

Eval Board: Manual

635.9 KB

EN

Eval Board: Manual

December 01, 2019

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