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Translators | MC100LVELT20

LVTTL/LVCMOS to Differential LVPECL Translator

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Datasheet

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Overview

The MC100LVELT20 is a 3.3 V TTL/CMOS to differential PECL translator. Because PECL (Positive ECL) levels are used, only +3.3 V and ground are required. The small outline SOIC−8 package and the single gate of the MC100LVELT20 makes it ideal for those applications where space, performance, and low power are at a
premium.
The 100 Series contains temperature compensation.

  • Single ended to differential level translation.

  • 390 ps Typical Propagation Delay
  • Maximum Input Clock Frequency > 0.8 GHz Typical
  • Operating Range VCC = 3.0 V to 3.6 Vwith GND = 0 V
  • PNP TTL Input for Minimal Loading
  • Pb-Free Packages are Available

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MSL Type

MSL Temp (掳C)

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Input Level

Output Level

VCC Typ (V)

fMax Typ (MHz)

tpd Typ (ns)

tR & tF Max (ps)

Reference Price

MC100LVELT20DR2G

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CAD Model

Pb

A

H

P

SOIC-8

751-07

1

260

REEL

2500

Y

1

TTL

ECL

3.3

1000

0.37

225

Price N/A

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Reliability Data

Die Related Summary Data

Device: MC100LVELT20DR2G

Equivalent to wafer fab process: MOSAIC

Product Technology

Product Technology

Equivalent Device-Hours

MTBF/MTTF in Hours

FITS

MOSAIC

0

476668904

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Re-calculate Data

Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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